School of Engineering Department of Electronic and Computer Engineering 155 Open-Source Digital Integrated Circuit Design and Tapeout Supervisor: ZHANG Yihan / ECE Student: KALAM Tayeeb Bin / ELEC Course: UROP 1000, Summer This project involves designing a digital circuit in Verilog and submitting it to Tiny Tapeout for fabrication as an ASIC (Application-Specific Integrated Circuit). The report focuses on development and implementing a traffic light controller using the fundamentals of state machine architecture in Verilog. This report includes an introduction to logic designs, truth tables, and the implementation in Verilog, along with verification methodologies. The functional behaviour of the circuit will be written and verified, and the design will be synthesized and then submitted for manufacturing. The fabricated IC will be tested to ensure it performs the intended functions. The constructed IC will be tested to confirm that it behaves as planned. This report offers a comprehensive understanding of the entire IC design process. Open-Source Digital Integrated Circuit Design and Tapeout Supervisor: ZHANG Yihan / ECE Student: LI Zhuoxuan / CPEG Course: UROP 1100, Fall UROP 1000, Summer As a follow-up to my previous UROP project on the RTL design of an FFT processor, this work explores the physical implementation, the critical back-end part of digital integrated circuit design that enables logic-level ideas to work on silicon. The work utilizes a proprietary digital design kit and commercial EDA software to replicate an automatic synthesis and PnR process initially provided by an open-source platform. The replicated process releases the constraints of limited IO resources and deploys a more advanced toolkit, enhancing the efficiency, flexibility, and performance of the current FFT processor and future digital design. Open-Source Digital Integrated Circuit Design and Tapeout Supervisor: ZHANG Yihan / ECE Student: TAHMID Mir Ahnaf / ELEC Course: UROP 1000, Summer The goal of this UROP project is to design a Linear Feedback Shift Register (LFSR)-based stream cipher, integrated with transmitter and receiver modules, to simulate real-time encryption and decryption of 8-bit messages. It utilizes Verilog HDL to perform rigorous hardware simulation and verification to ensure that the modules operate correctly before fabrication. The design is intended to be implemented into a piece of silicon as an ASIC using the tiny tapeout platform. Hands-on testing is to be conducted once the ASIC is shipped, and the functionality of the hardware will be evaluated and compared with the results previously obtained during the Verilog simulations. This report synthesizes the findings of the simulations and explores how specific design features could impact the performance of the final ASIC.
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