School of Engineering Department of Electronic and Computer Engineering 156 Open-Source Digital Integrated Circuit Design and Tapeout Supervisor: ZHANG Yihan / ECE Student: TSANG Tsun Yin / ELEC Course: UROP 1100, Summer This study delves into the implementation and performance evaluation of discrete PID controllers, with a focus on exploring the impact of a variety of discretization techniques and algorithms on system stability. Through Vivado, the study employs Verilog modeling to analyze the behavior of the discrete system across diverse configurations. Through examining these factors and their effects on system behavior, the research reveals that delays are introduced during feedback in the discrete system, indicating that certain PID enhancements effective in continuous systems may not seamlessly translate to discrete systems. Furthermore, the study highlights the impact of discretization on system stability. Ultimately, these findings underscore the importance of selecting appropriate discretization methods and algorithms to enhance both system stability and performance. Open-Source Digital Integrated Circuit Design and Tapeout Supervisor: ZHANG Yihan / ECE Student: YAU Man Kit Bosco / CPEG Course: UROP 1000, Summer This report presents the research on an electronic lock system using Verilog Hardware Description Language (VHDL). The system contains two parts: a lock module with all the logic and a testbench module to verify the function of the system. The lock includes a configurable password, allowing users to change the password after unlocking the system by entering the correct passcode sequence. The testbench module simulates the system in several scenarios: attempted unlock operations with a wrong and correct passcode, and changing of passcode. This report reviews the design and functionality of both modules and the results of simulation, proving that the system could handle secure access based on passwords. Open-Source Digital Integrated Circuit Design and Tapeout Supervisor: ZHANG Yihan / ECE Student: ZHU Quanhao / ELEC Course: UROP 1100, Spring UROP 2100, Summer This UROP provides hands-on experience in digital integrated circuit design using an open-source platform. Participants will build a small-scale digital circuit from logic description to tapeout and testing. This opportunity is ideal for individuals with a basic understanding of digital logic design who are interested in pursuing a career as a digital integrated circuit designer. My current research project involves designing a more complex device using Verilog language. The design will be simulated on a computer and sent to GitHub for fabrication. Once the chip is returned, I will proceed with the actual circuit testing. I have already submitted the design drawing to the website and am awaiting the chip's return to move forward with testing.
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